May 11th 2021
In this document I present the time-measuring performance characterization of the "fully digital TDC" to which, to be more specific, I refer to as the TDC V1 SW 28 10 19. First I briefly review the block diagram of this circuit and its working principle and then I proceed to the characterization process. The time resolution obtained is between 20 and 60 ps.
Table of contents
In this section I will describe some details about the TDC V1 SW 28 10 19 design as well as about the test setup employed for its characterization. This TDC was produced with UMC 110 nm technology. The whole system can be divided into three hierarchical blocks:
Each of these blocks contains the previous blocks, i.e. the test setup contains one test structure and the test structure contains four identical replicas of the TDC.
- The TDC V1 SW 28 10 19. This is the TDC design we are interested in.
- The test structure. This is the circuit implemented in the silicon which contains four identical TDC V1 SW 28 10 19 replicas and peripheral circuitry for the operation.
- The test setup. This is the whole measuring system composed of a Raspberry Pi, an FPGA, a specialized short-delay generation system and the test structure itself.
The TDC V1 SW 28 10 19 circuit
In it is shown the simplified block diagram of the TDC V1 SW 28 10 19 circuit. The heart of the circuit is the ring of inverters, highlighted in yellow. This is a closed path with an odd number of inverters, 21 in this case, which makes it an oscillator. As seen, the first of the inverters is a NAND gate, allowing to start or stop the oscillation. There is also a second chain of identical inverters, highlighted in green, which is not closed. This line has an extra inverter in the beginning. Additionally, there is a set of 21 memories, called
Simplified block diagram of the TDC V1 SW 28 10 19 design. In red the two input signals
SAFF_cell in the diagram, which are differential D flip-flopsThis flip-flop was specifically designed for this application., that basically store the difference of their inputs when
STOP signal is received. Finally, there is a 7 bit counter attached to the output of the last inverter in the non closed chain.
STOP and in blue the two output buses
The working principle
The working principle of this circuit is simple. Initially both
STOP signals are at a low value. In this case the ring of inverters (yellow) is in the state
1010...01 and the non closed chain (green) in state
0101...10. The circuit is in a stationary state. When the
START changes to a high state the NAND gate becomes a NOT gate and the state of the ring (yellow) is not stable anymore. It starts to oscillate by propagating a "wave of identical consecutive states", i.e. first it changes to
0010...01, after the propagation time it changes to
0110...01, and so on. The same happens with the non closed (green) chain of inverters. Each time the output of the last inverter in the non closed (green) chain commutes, the counter increments in one, registering a complete loop in the ring of inverters. In some moment in time the
STOP signal changes to a high state and in this moment the state of the two chains of inverters is freezed by the
SAFF_cell modules and the counter stops counting. Thus, the status of the circuit is freezed. By knowing the propagation time of the NOT gates, the conversion from the state to a time is direct and a measurement of time between the
STOP signals is obtained.
Note that each of the
SAFF_cell blocks in has the inputs switched. As far as I know the only reason for this is to have a "more beautiful" reading in the
SAFF bus. For example, instead of having an output of the form
0101101... we invert each odd bit and this becomes
0000111.... In this way it is easier to visualize in which position "the wave" is.
The test structure
The test structure implemented, i.e. the piece of silicon, contains four identical replicas of the TDC V1 SW 28 10 19 circuit. The (simplified) block diagram of the test structure is shown in . As can be seen all the TDCs share the same
Simplified block diagram of the test structure implemented. The test structure contains four identical replicas of the TDC V1 SW 28 10 19 design which block diagram is shown in .
STOP signals, and the only additional circuitry is a mechanism to select each of the four outputs via the
SEL selection bus. This selection is done during the readout process, time after the time measurement has finished.
😡 During the characterization procedure a bug was found in the silicon. In the output selection mechanism (see ) the four
COUNT bits are short-circuited among them and always connected to the output, independently of the
SEL value. Despite there is not an easy solution to this problem, a workaround was found to still be able to characterize the TDC V1 SW 28 10 19 design.
The test setup
Finally, in this section I will describe the outermost block which is the test setup. A simplified block diagram is shown in . In the rightmost part we find the test structure, described previously. Next, going from right to left, we find the delay module which is a board that contains two SY89296 delay chips. This delay module provides the
Simplified block diagram of the test setup. The block diagram of the test structure is shown in .
STOP signals with an arbitrary delay between -10 ns and 10 ns in steps smaller than 10 ps and fluctuations smaller than 5 ps (more details will be given in ). The rest of the signals from the test structure interface directly with an FPGA which was specifically configured for this applicationFor the record, the code used to program the FPGA for this work can be found in this repo, specifically in the commit fe27162759e35888a1b5c73677af94f15d5e2ab5.. The FPGA is controlled by a Raspberry Py which runs software developed specifically for this workAgain, for the record, the code used in the Raspberry Pi can be found in this repo in the commit 24143785a4c96a2dd802be2f7d97497134f91e5e.. The last element in the test setup, in the leftmost part, is me 🤓.
Test setup calibration
Before proceeding with the characterization of the test structure a calibration procedure was performed. The setup was placed in a laboratoryOur lab at G floor. with the ambient temperature controlled during the complete period of both calibration (of test setup) and characterization (of test structure). For this calibration, the test structure was replaced by an oscilloscopeLeCroy WaveRunner 640Zi sampling at 40 Gs/s. as shown in . The
Simplified block diagram for the calibration of the test setup. The setup is the same as the one used for characterizing the test structure () but the test structure was replaced by an oscilloscope measuring the
STOP signals produced by the delay module were measured with the oscilloscope and the time difference at a fixed voltage threshold was computed. This calibration procedure allowed to compensate for known deviations from the ideal behavior of the delay module as well as to know the systematic error introduced by the setup.
The results of the calibration procedure prior to the characterization of the test setup are shown in . The measured delay follows a Gaussian distribution . In the two plots shown in we find the difference between the mean of this distribution and the set delay in the left and the standard deviation of this distribution in the right, as functions of the set delay. The quantity we are more interested in here is the fluctuation of the delay. This quantity seems to be on the order of 4-4.5 ps for the whole range of delays. This number contains both the systematic of the test setup and the one from the oscilloscope. To get an estimation of the contribution from the oscilloscope itself, a 50 Ω "T" splitter was used to connect a single output from the test setup in the two inputs of the oscilloscope and measure the time difference in the same way. During this measurement the settings in the oscilloscope were left unchanged. A value of 4.8 ps was obtained, showing that most of the fluctuations shown in (right plot) are coming from the oscilloscope. As a result I am forced to consider that the fluctuations in the time difference between the
STOP signals is negligible throughout this work.
Results of the calibration of the test setup soon before proceeding with the characterization of the test structure. Left: Calibration mean error defined as the difference between the set delay and the average of the measured delay. Right: Delay fluctuations defined as the standard deviation of the measured delay.
Post characterization check. The calibration-check procedure was repeated after the characterization of the TDC structure to ensure that the system was still performing as expected. The results obtained are almost identical to the ones in . ✅
For the characterization process the setup was assembled as in taking care of modifying as least as possible the configuration with respect to the calibration procedure in order to not introduce unwanted effectsThis setup was observed to change its calibration due to environment effects in the past . For this characterization the environment was kept almost untouched, for example the oscilloscope used for the calibration procedure was left untouched next to the setup even when unused during the measurements.. In pictures of the setup during the characterization are shown.
Pictures of the test setup. The oscilloscope used for the calibration procedure was left at all the time next to the setup, even when not used, to maintain the environment as close as possible to the calibration setup.
The characterization proceeded as follows:
This process was repeated enough (around 3.5 million) times in order to obtain sufficient statistics. A fraction of the results are shown in . In this plot we only see results from a single TDC structure (TDC 2), the others look similar with the exception of TDC 1 which seems to be brokenThis TDC alone has an additional problem of unknown origin apart from the bug found in the output selection mechanism. The remaining three TDCs performed within the expected., and the time range was limited to about 500 ps though the data extends up to 10 ns. Each distribution shown in this figure corresponds to the time distribution of a particular output of the circuit. The notation used in the legend of this plot is
- A random time between 0 and 10 ns was chosen.
- The delay module was configured to produce such a time difference between the
STOP signals were produced thus running the TDC structure.
COUNT outputs of each of the four TDCs in the test structure were read.
COUNT is represented by an integer decimal number and
SAFF by the corresponding binary sequence. Thus, for example, the first output we find is
0|000000000000000000001 which means that the read value for the counter was
0 and for the ring of inverters the value was
Temporal distribution of each of the different outputs obtained from the TDC V1 SW 28 10 19 circuit. The notation in the legend is
SAFF are the buses shown in . To ease visualization you can enable/disable traces by clicking in the legend.
In this plot we can explore the data in a very crude but intuitive way. For example, if we chose a single output and isolate its trace by double clicking in the legend we see that all the occurrences of such output are very constrained in time, as expected. We can also see that the distributions are not identical between one another, for example the distribution of
The mean value for each of the distributions (the ones in ) was computed and is shown in . We see that the mean time is linear with the outputs, which is expected ✅. If we focus in the region with outputs between
0|000000000000000000011 (the first two in the legend) has a different width. Some sequences, for example
0|00000000000111111111, show a very peculiar bimodal distribution. This effect is due to the existence of "forbidden times" in the test setup, for some reason some delay values cannot be generatedIt is not yet known with certainty what is th ereason for this, but it is probably a bad implementation of the algorithm that defines the configuration of the delay module given an arbitrary delay value.. This is evident if we focus on the trace with legend All events without filtering.
16|xxxx, where the linear behavior is observed, we note some "periodic perturbations" in the form of negative peaks to this line. The reason for this is well understood and originates in the fact that the counter changes its output while the change of inverters has not yet changed. Thus, for each value of the counter, the last state of the chain of inverters and the first one are degenerated. A solution to this is to add a single bit counter attached to another point of the chain of inverters, for example in the middle, to break the degeneracy.
Mean time for each sequence. The mean time for each sequence is just the mean of each distribution shown in .
It can also be appreciated in that the three TDCs "run at the same speed" in the sense that the slope of the three lines cannot be distinguished from one another.
To further proceed with the analysis, a value of time resolution was assigned to each different output. Since the distribution of the sequences in time tends to be rather uniformSee for example the distribution of
Time resolution of each output. The time resolution shown here is defined as the difference between the q95% and the q5% quantiles for the temporal distribution of each sequence, as shown in .
0|000000000000000011111 in ., instead of using the standard deviation $\sigma$ as a measure for the time resolution, it was defined as the difference between the 95 % and the 5 % quantiles. This quantity is shown in . As can be seen, most of the values of time resolution accumulate below 50 ps and there are some isolated and periodic peaks with values close to 1 ns. These peaks correspond to the degenerated outputs mentioned previously; the same output is found when the counter commutes from $n-1$ to $n$ and when the counter commutes from $n$ to $n+1$, thus producing a distribution with two peaks separated by the counter period. As this problem is already understood, we can now focus in the region with time resolution below 60 ps. In the plot in a moving average for each TDC was added to ease the visualization. In these averages we see that for outputs between
16|xxxx there is a tendency to increase, and then there is a sudden decrease. The increase, which denotes a degradation in the time resolution, is expected because the fluctuations in the commutation time of the inverters.
To conclude with the analysis, the distribution of the time resolution from was plotted. The graph is shown in . The bins beyond 1 ns can be ignored as they correspond to the degenerated outputs. If we zoom in horizontally in the region below 80 ps we see that the worse time resolution is, for only a single output, 70 ps. The peak resolution is slightly below 20 ps and the mean time resolution around 30-40 ps.
Distribution of the time resolution shown in .
Required space (surface)
In it is graphically shown the required space to implement the TDC V1 SW 28 10 19 and compared to a 50×50 µm2 pixel. As can be seen, it does not fit.
Diagram comparing the size of a 50×50 µm2 pixel with the area required for the current implementation of the TDC. As can be seen, this implementation does not fit in such a pixel.
Conclusions and discussion
The TDC V1 SW 28 10 19 test structure was characterized in terms of its performance in time measurements. Its working principle was understood and a specialized test setup was configured for the characterization. A careful calibration was done and checked on the test setup before the measurements to the TDC, and this calibration was revised again after the measurements were completed to verify the correct functioning of the system. During the characterization process a bug was found in the circuit implemented in the silicon, which affects the least significant bit of the counter. Despite this complication it was still possible to proceed with the characterization.
For this test structure the time resolution is better than 60 ps, with a typical value of around 30 ps. The range of time measured spans between 0 and 10 ns. The time resolution was observed to degrade as the measured time increases; however this degradation seems to be small, in the order of 10 % for the whole measured range.
It is still pending to determine the power consumption of this design. The current implementation does not fit in a 50×50 µm2 pixel.