Future HEP experiments will require not only spatial but also **temporal resolution** in the tracker

The so called *4D pixels* are under strong development to provide accurate time+space tracking of Minimum Ionizing Particles (MIPs).

A number of technologies under development

- Inverse LGAD (iLGAD)
. - Trench Isolated LGAD (TI-LGAD)
. - AC Coupled LGAD (AC-LGAD)
.

Add new capability with Time to Digital Converters (TDC) to digitize the timing information.

- TDC technology already exists.
- Has to be adapted to the constraints in HEP.
- Fit within a pixel.
- Low power consumption.
- Radiation tolerant.

Long term goal: "Full ASIC" for 4D pixels.

**Today** I will focus on the timing digitizer, **TDC**.

A closed chain of inverters + a counter:

3 designs have been **produced and tested** based on this concept:

- Fully digital TDC. UMC 110 nm technology.
- Semi analog TDC. L Foundry 110 nm technology
This design was also produced with UMC110 technology. The production with LF110 technology, however, yields better results and this one is discussed in this talk. . - Fully analog TDC. (Not discussed today.)

- Fast inverters. 21 in total.
- Ring is digitally sampled.

`START`

and`STOP`

at low level. The ring is open; no oscillation.`START`

changes to high. The ring is closed; begins to oscillate.- The counter counts number of full loops.
`STOP`

changes to high. The state of the system is registered by the flip-flops and the counter.

- Slower inverters with special design. 9 inverters in total.
- Ring is sampled in an analog way.

`START`

and`STOP`

at low level. Ring does not oscillate.`START`

changes to high. The ring starts to oscillate (it is properly initialized, not shown in the block diagram).- The counter counts the number of full loops.
`STOP`

changes to high. The inverters are "analogly frozen" in whatever state they were. The one inverter that was commuting is frozen in an intermediate state.

We can view each TDC as a black box:

A specialized test setup was assembled.

- Raspberri Pi: Automates measurement routines.
- FPGA: Controls hardware.
- Delay module: Produces
`START`

and`STOP`

signals with arbitrary time difference (-10 to 10 ns in steps of about 1 ps).

A picture of the setup (human not shown 😁):

- The time $\Delta t = t_\text{START} - t_\text{STOP}$ was measured with the TDC many times, with different values of $\Delta t$, to get enough statistics.
- For each $\Delta t$ the output of the TDC was recorded.

Raw data shown in the histogram below.

- The notation is
`COUNT[:]|INV[:]`

. - Distribution: Uniform with small tails.

We can think of this as an imperfect ruler:

- The "ruler" is "dense", i.e. there are no empty gaps.
- For each bin in this "imperfect ruler" (i.e. for each output of our TDC) we can define its own resolution.
- Distributions tend to be uniform.

In view of this, I will look at the following quantities:

- Mean.
- Standard deviation $\sigma$.
- Width of the distribution measured as $q_{95\text{ %}} - q_{5\text{ %}}$ where $q_x$ is the $x$ percent quantile.

- Linear (as expected).

This plot shows $\sigma$ and $q_{95\text{ %}} - q_{5\text{ %}}$ together.

- Moving averages increase for higher times. Expected because fluctuations in propagation delay of inverters are accumulative.

Let's see the distribution of the temporal dispersion of the outputs:

Temporal resolution for this TDC:

- Using $q_{95\text{ %}} - q_{5\text{ %}}$ (i.e. "full width"):
- All widths are $\lt 60 \text{ ps}$.
- "Typical value" of $30 \text{ ps}$.

- Using $\sigma$ (standard deviation):
- All $\sigma$'s are $\lt 20 \text{ ps}$.
- "Typical value" of $10 \text{ ps}$.

Raw data looks like this:

- The counter counts each falling edge of
`INV[8]`

. `INV[8]`

has different amplitude due to the counter input impedance.

Let's normalize all the `INV[:]`

signals and invert the odd ones:

Now we digitize them with a "low resolution ADC":

Digitized `INV[:]`

now looks like this:

- 1 bit (two levels):
`INV[:]`

bus will look like:`000011111`

. - 2 bit (four levels):
`INV[:]`

bus will look like:`000123333`

. - 3 bit (eight levels):
`INV[:]`

bus will look like:`001234567`

. - Etc.

This procedure on real data:

1 bit

2 bit

3 bit

Repeat the same analysis as for the "fully digital" varying the number of discrete levels.

q_{95 %} - q_{5 %}

Standard deviation

- Degradation of time resolution as time goes by; again expected due to the accumulative fluctuations in propagation delay.
- Time resolution improves by adding bits ✅.

Temporal resolution for this TDC:

- Using $q_{95\text{ %}} - q_{5\text{ %}}$ (i.e. "full width"):
- 1 bit: $\lesssim 70 \text{ ps}$.
- 2 bit: $\lesssim 40 \text{ ps}$.
- 3 bit: $\lesssim 30 \text{ ps}$.

- Using $\sigma$ (standard deviation):
- 1 bit: $\lesssim 40 \text{ ps}$.
- 2 bit: $\lesssim 20 \text{ ps}$.
- 3 bit: $\lesssim 10 \text{ ps}$.

Reference pixel of 50×50 µm^{2}

Current implementation:

- 21 inverters and 7 bits counter.
- Up to $\approx 150 \text{ ns}$.
- Does not fit in a 50×50 µm
^{2}pixel.

Current implementation:

- 9 inverters and 5 bits counter.
- Up to $\approx 100 \text{ ns}$.
- Fits fine in a 50×50 µm
^{2}pixel.

Will require more complicated readout logic, however this is in the periphery.

- An analog front end circuit was designed and produced, though not yet tested.
- Projected prototype:
- Pixel size: 100×100 µm
^{2}. - 30×30 pixels.
- Interface it with real TI-LGAD sensors (in production).

- Pixel size: 100×100 µm

- Two TDC designs were produced, tested and studied:
- Fully digital TDC: Fast inverters, digital readout.
- Semi analog TDC: Slower inverters, semi-analog readout.

- Their performance was studied.
- Fully digital TDC: $\lesssim 60 \text{ ps}$ "full width" time resolution, $\sigma \lesssim 20\text{ ps}$.
- Semi analog TDC: $\lesssim 30 \text{ ps}$ "full width" time resolution, $\sigma \lesssim 10\text{ ps}$.

- Semi analog design fits well in 50×50 µm
^{2}pixel. - Power consumption and radiation hardness studies are pending.